1. Field of the Invention
The present invention relates to a semiconductor device provided with a single-ended sense amplifier that senses data on a transmitted line, and particularly relates to a semiconductor device in which data stored in a memory cell is read out to a bit line and amplified by the single-ended sense amplifier.
2. Description of Related Art
In recent years, as miniaturization of memory cells has been advanced in semiconductor memory devices such as DRAM, it becomes difficult to obtain a sufficient capacitance of a capacitor included in each memory cell. Therefore, a sense amplifier capable of reliably amplifying a minute signal voltage readout from the memory cell is desired. For example, a charge transfer type sense amplifier is known as an example of the sense amplifier suitable for amplifying the minute signal voltage (for example, refer to the following Patent References 1 to 4). In general, a differential type sense amplifier is conventionally used, which is configured to receive the signal voltage of a bit line and a reference voltage respectively so as to perform a differential amplification.
The sense amplifier is configured by using field-effect transistors (for example, MOS transistors), and variation of threshold voltages of the MOS transistors needs to be considered in order to ensure a normal operation of the sense amplifier. In the semiconductor device, a decrease in size and an increase in capacity generally cause a tendency to increase a random variation distribution of threshold voltages of a large number of MOS transistors in a chip. Various proposals have been conventionally made concerning methods for compensating an offset due to unbalance of threshold voltages of a pair of MOS transistors in the above differential type sense amplifier. For example, the Non-Patent Reference 1 discloses an offset compensation technique for compensating an input offset (a potential offset of an input node) due to the random variation distribution of the threshold voltages of the MOS transistors in the chip by setting 16 kinds of reference voltages for each 32 sense amplifiers.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2000-195268 (U.S. Pat. No. 6,154,402)    [Patent Reference 2] Japanese Patent Application Laid-open No. 2002-157885 (U.S. Pat. No. 6,594,187)    [Patent Reference 3] Japanese Patent Application Laid-open No. H11-16384    [Patent Reference 4] Japanese Patent Application Laid-open No. 2007-73121    [Non-Patent Reference 1] S. Cosemans, W. Dehaene and F. Catthoor, “A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers,” IEEE J. Solid-State Circuits, vol. 44, Issue 7, pp. 2065-2077, July 2009.
In general, it is more desirable to employ a single-ended sense amplifier to which the reference voltage is not required to be inputted than to employ the differential type sense amplifier from perspectives of a high density arrangement of memory cells and a reduction in circuit scale. However, the above conventional offset compensation technique associated with the random variation of the threshold voltages of transistors is adapted to the differential type sense amplifier (configured to have two input terminals, one of which is a first input terminal receiving signal data of a transmission line, and the other of which is a second input terminal receiving a reference signal for sensing), and cannot be adapted to the single-ended sense amplifier (configured to have one input terminal). This is because the single-ended sense amplifier does not have a terminal supplied with the reference voltage directly associated with a sense node of the sense amplifier. Further, the Non-Patent Reference 1 discloses a method applied to a configuration in which a relatively small number (32) of sense amplifiers are arranged in a semiconductor memory, and the method optimizes the reference voltage for each sense amplifier, which cannot be adapted to a configuration in which a large number of sense amplifiers are arranged in the semiconductor device such as a large capacity DRAM. As described above, in case of configuring a semiconductor device by employing the single-ended sense amplifiers, there has not been proposed a method to effectively prevent a performance deterioration of the sense amplifier due to the variation distribution of the threshold voltages of field-effect transistors (for example, MOS transistors).